
import parametr_5::*;
module verilog_5 (
//--------------------------------------------

input wire                       reset,
input wire                         clk,

 
input wire [parametr_1-1:0]          U,
input wire [parametr_1-1:0]          S,
input wire [parametr_1-1:0]          H,



//---------------------------------------
output reg  [parametr_2-1:0]          data5_out); 

reg  [parametr_1-1:0]          P;
reg  [parametr_2-1:0]          Q;
reg  [parametr_1-1:0]  c_endtime;



// zadanie 5

always @(negedge reset or posedge clk)
begin 
	if (!reset)
	begin
		        Q           <= 0;
                P           <= 0;
                c_endtime   <= 0;
                data5_out   <= 0;
	end
	else
	begin
		Q                          <=S*H;
		P                            <=U;
        c_endtime                    <=P;
		data5_out          <=Q+c_endtime;
		
	end
	
	
end


endmodule 